//向FIFO写入数据
// .clk(clk),                    // input wire clk
//.din(din),                    // input wire [15 : 0] din
//.wr_en(wr_en),                // input wire wr_en
//.full(full),                  // output wire full
//.almost_full(almost_full),    // output wire almost_full  
//.empty(empty),                // output wire empty
module write_operate (
    input       wire                clk_50m,
    input       wire                rst_n,
    input       wire                empty,
    input       wire                full,
    output      reg     [15:0]      din,
    output      reg                 wr_en
);

    reg     [15:0]      data;       //作为要写入的数据
    
    //让 data 变动
    always @ (posedge clk_50m or negedge rst_n) begin
        if (rst_n == 0)
            data <= 1;
        else
            data <= data + 1;
    end
    
    //做一个标志位，当fifo 非空非满 时，标志位为1 ，
    reg flag = 0;
    always @ (posedge clk_50m or negedge rst_n) begin
        if (rst_n == 0)
            flag <= 0;
        else if (empty == 1'b1)
            flag <= 1'b1;         //当fifo 空了，flag 为 1，不空也不满的时候 flag 还继续为 1
        else if (full == 1'b1)
            flag <= 1'b0;         //当 fifo 满了，flag 为0 ，不满也不空时候，flag 还继续为 0
        else
            flag <= flag;
    end
    
    //检查full ，如果满，则不写入输入。不满，则写入
    always @ (posedge clk_50m or negedge rst_n) begin
        if (rst_n == 0)//复位
            begin
                wr_en <= 1'b0;
                din <= 16'b0;
            end
        else if (full == 1'b1)
            begin
                wr_en<=0;
            end
        else if (flag)
            begin
                din <= data;        //要写入的数据
                wr_en <= 1'b1;
            end
    end

endmodule
